PURPOSE: To suppress the increase of the electric current at a write time, even in the case that the data bus becomes multi-bits.

CONSTITUTION: The read and write control signal corresponded to the chip enable signal/CE outputted from a read/write control circuit 20, is divided by the division signal DV outputted from a counter 24 in AND circuits 21, 22. A first and a second write circuits 17, 18 write alternately the data in a memory cell array 11 by the division signal DV. Then even in the case that the data bus becomes multi-bits, the increase of the electric current at a write time can be suppressed compared with the case that the data is written en bloc.