To provide a tiny nonvolatile semiconductor memory which is improved in the cut-off characteristic of a selection gate transistor, and to provide its manufacturing method and system therefor.
Word lines WL1, WL2,...,WL32 are arranged orthogonally to bit lines DQ in a NAND type flash memory cell unit, and a source line CS is connected electrically in common. Two selection gate lines SGD1, SGD2 of bit line side selection transistors, and two selection gate lines SGS1, SGS2 of source line side selection transistors are separately short-circuited every 64 lines of the bit lines to form bit line side selection gate lines SGD and source line side selection gate lines SGS. The memory cell unit can be applied for an AND type and a divided bit line NOR type as well, and the number of the selection gate lines may be plural. Different voltages may be given to the plurality of selection gate lines.
SAKUI YASUSHI
TAKEUCHI YUJI
SHIRATA RIICHIRO
MORI SEIICHI
HASHIMOTO KOJI
KUJI TATSUAKI
Yasuo Miyoshi
Iwa Saki Kokuni
Kawamata Sumio
Nakamura Tomoyuki
Masakazu Ito
Shunichi Takahashi
Toshio Takamatsu