Title:
NONVOLATILE SEMICONDUCTOR MEMORY
Document Type and Number:
Japanese Patent JP2009076137
Kind Code:
A
Abstract:
To provide a nonvolatile semiconductor memory which has high read-out operation speed.
In switching circuits 10a, 10b of this MRAM, when a corresponding column selection line CLS0 is set to be a "H" level and also when a memory array 1 is selected, bit lines BLA0, BLA0; BLB0, BLB16; BLA16, BLA16; BLB0, BLB16 are connected respectively to input nodes N1 to N4 of comparing circuits 31 and 32, and when the corresponding column selection line CSL0 is set to be the "H" level and when a memory array 2 is selected, bit lines BLA0, BLA16; BLB0, BLB0; BLA0, BLA16; BLB16, BLB16 are connected respectively to the nodes N1 to N4. Parasitic capacity of the input nodes N1 to N4 of the comparing circuits 31 and 31 therefore can be made equal.
Inventors:
KAWAGOE TOMOYA
Application Number:
JP2007243673A
Publication Date:
April 09, 2009
Filing Date:
September 20, 2007
Export Citation:
Assignee:
RENESAS TECH CORP
International Classes:
G11C11/15; H01L21/8246; H01L27/105; H01L43/08
Domestic Patent References:
| JP2004103060A | 2004-04-02 | |||
| JP2002222589A | 2002-08-09 |
Attorney, Agent or Firm:
Kuro Fukami
Toshio Morita
Yoshihei Nakamura
Yutaka Horii
Hisato Noda
Masayuki Sakai
Nobuo Arakawa
Toshio Morita
Yoshihei Nakamura
Yutaka Horii
Hisato Noda
Masayuki Sakai
Nobuo Arakawa
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