PURPOSE: To realize the high integration density of a memory cell and to enhance a readout speed and a write characteristic by a method wherein semiconductor regions which are composed of high impurity concentration regions and low impurity concentration regions are formed at the upper part of a plurality of pillar-shaped parts and semiconductor regions which are composed of high impurity concentration regions are formed in a semiconductor substrate in parts between the plurality of pillar-shaped parts.

CONSTITUTION: A plurality of pillar-shaped parts 1a are formed in a semiconductor substrate 1; floating gates FG are formed at the outer circumference at the bottom part of the plurality of pillar-shaped parts 1a via gate insulating films 2. Semiconductor regions which are composed of high impurity concentration regions 4 and low impurity concentration regions 4a are formed at the upper part of the plurality of pillar-shaped parts 1a; semiconductor regions which are composed of high impurity concentration regions are formed in the semiconductor substrate 1 between the plurality of pillar- shaped parts 1a. Consequently, an area occupied per memory cell can be reduced, and the current driving ability of a memory transistor can be increased. Thereby, the high integration density of a memory cell can be realized, a readout speed can be enhanced and a write characteristic can be enhanced.