To provide a nonvolatile semiconductor storage device capable of shortening the time for verifying operation while correcting variance in thresholds between memory cell transistors in a simultaneous writing operation after excessive erasure.
At time t3, a voltage of 6V is applied to all word lines WL1 to WLn, and very weak writing operations which use channel hot electrons are simultaneously started for all memory cells connected to a bit line BL2. At time t9, a voltage of about 2V is applied to the word line WL1 to start a verifying operation for an optional one memory cell connected to the word line SL1. A series of these very weak writing and verifying operations are repeated until the threshold voltage of this memory cell reaches 2V of an erasure state.
OISHI TSUKASA
Toshio Morita
Yoshihei Nakamura
Yutaka Horii
Hisato Noda
Masayuki Sakai