To provide a nonvolatile semiconductor storage device which adjusts timings of data input for a page buffer and data determination in a latch of the page buffer, in association with the number (number of on-cell) of data "1" in one page.

The nonvolatile semiconductor storage device includes: a memory cell array in which a plurality of bit lines and a plurality of word lines intersect each other, respectively, and nonvolatile memory cells MC0 to MC4 are arranged in the intersections between the bit lines and the word lines; a page buffer group 13 which is provided on each of bit lines BL0, BL1, ... and includes a latch for storing data to be written in the memory cell selected by word lines WL0 to WL4 or data that has been read from the memory cell; and a control circuit 20 for controlling data input time from the bit line to the page buffer and determination time by the latch of the input data according to a voltage level of a common source line CSL provided commonly to the source sides of the plurality of bit lines, in an operation of reading data from the memory cell.