PURPOSE: To improve erasing characteristics and write characteristics, by increas ing impurity concentration in a third semiconductor region constituting a drain region of a memory transistor, lowering the breakdown voltage of the third semiconductor region, and elevating the breakdown voltage of a first semiconduc tor region organizing a source region.

CONSTITUTION: A memory transistor Q1 is constructed by respectively using first and third semiconductor regions as a source region 5 and a drain region 6, and a selective transistor Q2 is constituted by separately employing third and second semiconductor regions as the source region 5 and the drain region 6. In the memory transistor Q1, impurity concentration in the third semiconduc tor region is increased and breakdown voltage thereof is lowered, thus easily generating hot electrons. The hot electrons are injected into a floating gate electrode FG, thus improving erasing characteristics. On the other hand, break down voltage on the first semiconductor region side is elevated, thus enhancing write characteristics. Accordingly, erasing characteristics and writing characteristics can be improved.