To provide a nonvolatile semiconductor storage for reducing the occupation area of a capacitive element.
The nonvolatile semiconductor storage has: a capacitive element region C for composing capacitive elements Cp1-Cp3. The capacitive element region C includes: a plurality of capacitance lines CpL1-CpL4 laminated on a semiconductor substrate; and a plurality of interlayer insulating layers formed between the upper and lower portions of the plurality of capacitance lines CpL1-CpL4. One (CpL2, CpL4) of the adjacently laminated capacitance lines is connected to prescribed potential. The other (CpL1, CpL3) of the adjacently laminated capacitance lines is connected to the ground potential. The adjacently laminated capacitance lines CpL1-CpL4 and the interlayer insulating layers among the capacitance lines CpL1-CpL4 compose the capacitive elements Cp1-Cp3.
NITTA HIROYUKI
JPH08264721A | 1996-10-11 | |||
JPH06338602A | 1994-12-06 | |||
JPH1032269A | 1998-02-03 | |||
JP2000514243A | 2000-10-24 | |||
JP2002141469A | 2002-05-17 | |||
JP2004200504A | 2004-07-15 | |||
JP2007317874A | 2007-12-06 |
Kazuhiko Tamura