PURPOSE: To enable reset operation to bit lines at the time of the data access of the identical bit line while connecting all the bit lines to constant potential through the reset transistor by temporarily turning all the reset transistor to a continuity state in response to the change when a word address signal is changed.
CONSTITUTION: An address change detection means 62, detecting the change of an address signal to select the word line, and a continuity means 63, conducting reset transistors 57 to 60 in response to address change detection, are provided. In the case of the data access of the identical bit line, only the word address signal (ADW) is changed so that the change of the ADW can be detected by an ATD circuit 62, and the continuity means 63 turns all the reset transistors 57 to 60 to the continuity state in response to the detection result (SAO/1P) of the ATD circuit 62. Thus, the bit lines can be reset at the time of the data access of the identical bit line, and the stabilization of the data reading operation can be realized.
IKUTA NOBUO
TERUI AKIRA
KIMURA MASAKAZU
