Title:
THIN FILM TRANSISTOR AND MANUFACTURE THEREOF
Document Type and Number:
Japanese Patent JP3181692
Kind Code:
B2
Abstract:
PURPOSE: To reduce parasitic capacitance among source-drain electrodes and a gate electrode and leakage currents, and to obtain high speed properties while preventing a burden on a peripheral circuit.
CONSTITUTION: A source electrode 12a and a drain electrode 12b are formed onto a substrate 10, and parts of the electrodes 12a and 12b are coated with contact layers 14a, 14b. Insulator layers 16a, 16b are formed onto the source- drain electrodes 12a, 12b not coated with the contact layers 14a, 14b. An active layer 18 is shaped onto the substrate 10 between the contact layers 14a, 14b and onto the contact layers 14a, 14b and insulator layers 16a, 16b, and a gate electrode 22 is formed onto the active layer 18 through a gate insulating film 20. Accordingly, the insulator layers 16a, 16b are held among the superposition of the source-drain electrodes 12a, 12b and the gate electrode 22.
Inventors:
Hiroshi Takizawa
▲梁▼井 健一
Tsutomu Tanaka
▲梁▼井 健一
Tsutomu Tanaka
Application Number:
JP16870092A
Publication Date:
July 03, 2001
Filing Date:
June 26, 1992
Export Citation:
Assignee:
富士通株式会社
International Classes:
H01L29/78; H01L21/336; H01L29/786; (IPC1-7): H01L29/786; H01L21/336
Domestic Patent References:
| JP1219825A |
Attorney, Agent or Firm:
Yoshito Kitano