Title:
I/O回路
Document Type and Number:
Japanese Patent JP4823098
Kind Code:
B2
Abstract:
The I/O circuit 1 is provided with a first NMOS driver 10 having a drain connected to a pad, a second NMOS driver 11 arranged in an active area which differs from the first NMOS driver 10 and having a drain connected to a source of the first NMOS driver 10 and a source connected to a ground potential, a level converter converting a level of an internal power source potential to a level of a power source potential, and a first NMOS transistor 26 having a drain connected to one output terminal of the level converter, a source connected to a ground potential, and a gate connected to another output of the level converter, and wherein the drain of the first NMOS transistor is connected to the gate of the second NMOS 11.
Inventors:
Teruo Suzuki
Application Number:
JP2007038959A
Publication Date:
November 24, 2011
Filing Date:
February 20, 2007
Export Citation:
Assignee:
Fujitsu Semiconductor Limited
International Classes:
H03K19/003; H01L21/822; H01L27/04; H03K19/0175; H03K19/0185; H03K19/0948
Domestic Patent References:
| JP2006238365A |
Attorney, Agent or Firm:
Patent business corporation NEXT
Hiroto Tanaka
Hiroto Tanaka