Title:
OFFSET COMPENSATING CIRCUIT
Document Type and Number:
Japanese Patent JPS6080348
Kind Code:
A
Abstract:
PURPOSE: To decrease the storage time of offset and to reduce power consumption by sampling and holding the offset voltage of circuit of a pre-stage and subtracting the held value from the output signal of the circuit of pre-stage.
CONSTITUTION: A sample and hold circuit 6 samples a signal when no input signal (f) exists to store offset amount. When the input signal (f) having an offset is incoming, the offset amount stored in the sample and hold circuit 6 is subtracted from the signal by an analog adder 7 and a signal (g) not including any offset is obtained at the output. Thus, the storage time of offset is decreased and the power consumption is reduced.
Inventors:
TAKAHASHI YUTAKA
KURAISHI YOSHIAKI
ISHIKAWA MASAYUKI
KIMURA TADAKATSU
KURAISHI YOSHIAKI
ISHIKAWA MASAYUKI
KIMURA TADAKATSU
Application Number:
JP18821483A
Publication Date:
May 08, 1985
Filing Date:
October 07, 1983
Export Citation:
Assignee:
NIPPON ELECTRIC CO
NIPPON TELEGRAPH & TELEPHONE
NIPPON TELEGRAPH & TELEPHONE
International Classes:
H03F3/34; H03F3/347; H04L5/16; H04L25/06; H04L25/38; H04Q1/20; H04Q3/42; (IPC1-7): H04Q1/20
Domestic Patent References:
| JPS55110427A | 1980-08-25 | |||
| JPS52155040A | 1977-12-23 |
Attorney, Agent or Firm:
Uchihara Shin