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Title:
OFFSET VOLTAGE CONTROL CIRCUIT
Document Type and Number:
Japanese Patent JPS61175784
Kind Code:
A
Abstract:

PURPOSE: To decrease the number of control processes and to attain the control of an offset voltage at all times by controlling automatically the offset voltage of an integrator.

CONSTITUTION: A digital signal having a mark factor of 50%, for example, is applied to the integrator 5. The output voltage of the integrator 5 is converted into the digital voltage by a converter 8-3 via a multiplexer 8-1 and applied to an MPU7. The MPU7 reads out the offset voltage corresponding to the output voltage 0 stored in a ROM10 as long as the input voltage of the MPU7 is not equal to 0. The offset voltage is applied to the integrator 5 via a multiplexer 8-2 and a converter 9-2. When the output voltage of the integrator 5 is equal to 0, the control is through with the offset voltage. Then a latch circuit 9-1 self-holds the supplied offset voltage, and another integrator is selected to repeat the above-mentioned procedure. For the integrator 5 with which the control is through, the offset voltage held at the circuit 9-1 is converted into the analog voltage by a converter 9-2 and applied to an amplifier 5-1.


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Inventors:
MINOWA MORIHIKO
SAKANE TOSHIRO
Application Number:
JP1591785A
Publication Date:
August 07, 1986
Filing Date:
January 30, 1985
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H03F3/34; G06G7/184; G06G7/186; H03H15/00; H04B3/04; (IPC1-7): G06G7/184; H03F3/34; H03H15/00
Attorney, Agent or Firm:
Sadaichi Igita



 
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