Title:
ONE-CHIP MICROCOMPUTER INCLUDING MULTIPROCESSOR
Document Type and Number:
Japanese Patent JP3187117
Kind Code:
B2
Abstract:
PURPOSE: To completely execute the parallel execution processing of plural programs by a simple constitution without externally preparing a specific control circuit.
CONSTITUTION: This one-chip microcomputer 15 including a multiprocessor is provided with plural built-in processors 11 for reading out plural programs 1a in the order of priority, executing the programs 1a in parallel and mutually sending execution and interruption instructions based upon the programs, a memory access control means 12 for allowing the processors 11 to access an external main memory 1 in parallel, a synchronizing bus 13 for which is connected mutually in parallel to each processor 11 and transmits the execution and interruption instructions to respective processors 11, and an I/O control means 14 for allowing respective processors 11 to access plural I/O devices 9 in parallel when the processors 11 send their processing results to the external and constituted so as to control the parallel access of the processors 11 and execute the parallel processing of plural programs.
Inventors:
Naoki Fujii
Application Number:
JP5472392A
Publication Date:
July 11, 2001
Filing Date:
March 13, 1992
Export Citation:
Assignee:
Toshiba Corporation
International Classes:
G06F15/16; G06F9/52; G06F15/177; (IPC1-7): G06F15/16
Domestic Patent References:
| JP62210564A | ||||
| JP60254358A | ||||
| JP62152064A | ||||
| JP2244252A | ||||
| JP3257634A | ||||
| JP3144847A | ||||
| JP5887645A | ||||
| JP1121968A | ||||
| JP1270147A | ||||
| JP3172956A | ||||
| JP5267930A | ||||
| JP641048A |
Attorney, Agent or Firm:
Takehiko Suzue