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Title:
ONE-ADDITION/SUBTRACTION CIRCUIT
Document Type and Number:
Japanese Patent JPH06309148
Kind Code:
A
Abstract:

PURPOSE: To provide a one-addition/subtraction circuit capable of performing the one-addition/subtraction of multiple bits simultaneously and being operated at high speed.

CONSTITUTION: This circuit is equipped with a data inversion means 1501 which outputs the inversion signal of least significant bit of input digital data, plural input means which input the input digital data to a one-addition/substraction circuit 1502 and a data selection means 1503 as data at every N bits except for the least significant bit, plural one-addition/substraction circuits 1502 cascade- connected with each other and which increase/decrease digital data of N bits by one and output data of (N+1) bits, and output a carry/borrow signal to the next stage when carry or borrow is performed, and plural data selection means 1503 which output by switching the input digital data of N bits in each one-addition/subtraction circuit 1502 and output digital data, and it is possible to shorten computing time by increasing/decreasing the multiple bits by one and performing the one-addition/subtraction at high speed.


Inventors:
SHIRAISHI MIKIO
Application Number:
JP9613593A
Publication Date:
November 04, 1994
Filing Date:
April 22, 1993
Export Citation:
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Assignee:
TOSHIBA CORP
International Classes:
G06F7/50; G06F7/507; (IPC1-7): G06F7/50
Attorney, Agent or Firm:
Takehiko Suzue