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Title:
ONE-DIMENSIONAL MAPPING CIRCUIT
Document Type and Number:
Japanese Patent JPH09260952
Kind Code:
A
Abstract:

To provide a one-dimensional mapping circuit on an integrated circuit and to improve the state decision accuracy of circuit output by turning a CMOS source follower to the depletion mode and turning a CMOS inverter to an enhancement mode.

The CMOS inverter applies transmission characteristics with which an output voltage decreases against the increase of an input voltage. The CMOS source follower, for which the CMOS inverter is inverted between a power source and the GND, applies voltage characteristics with which an output voltage increases corresponding to the increase of an input voltage. Concerning the CMOS inverter and the CMOS follower, the input is commonly applied, the output is commonly connected, and non-linear input/output transmission characteristics synthesizing decrease and increase functions are provided. In order to control non-linearity from the outside, external biases are respectively applied. Since the CMOS source follower is set to the depletion mode and the CMOS inverter is set to the enhancement mode, channel sizes are equalized and the state decision accuracy is made equal.


Inventors:
SHONO KATSUFUSA
Application Number:
JP10875496A
Publication Date:
October 03, 1997
Filing Date:
March 26, 1996
Export Citation:
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Assignee:
MICRO TECHNOL KK
International Classes:
H01L29/78; G09C1/00; H01L21/8238; H01L27/092; H03B29/00; H03K19/0948; H04L9/26; (IPC1-7): H03B29/00; G09C1/00; H01L29/78; H03K19/0948; H04L9/26