PURPOSE: To make calculation efficient by reading out contents of a counter for overflow to correct overflow.
CONSTITUTION: Data strings are inputted to input terminals 9 and 10 and are multiplied in a multiplier 1, and the result is inputted to the first shifter 2. Since contents of a counter 7 is "0" at the first, the shifter 2 outputs the multiplication result to an operator 3 as it is, and contents stored in a register 5 and the output of the shifter 2 are added. Since contents of the register 5 are cleared to "0" at first, overflow is not generated. If the n-th overflow is generated when data strings are inputted after input of several data strings, this overflow is detected by a detector 6, and data of a prescribed format is stored in the register 5 because the second shifter 4 shifts data right by one bit by the designation of a control circuit 8. At this time, the counted value of the counter 7 becomes (n), and the control circuit 8 designates the shifter 2 to shift data right by n-number of bits, and contents of the shifter 2 are inputted to the operator 3 with the same format as contents of the register 5 and are added to contents of the register 5.
JPH01155434 | EXCEPTION PROCESSOR |
JPS56114046 | REPETITIVE OPERATION SYSTEM |
JPH03257618 | ARITHMETIC SYSTEM FOR DECIDING CALCULATING ERROR |
JPS605338A | 1985-01-11 |