Title:
OPERATIONAL AMPLIFIER
Document Type and Number:
Japanese Patent JP3131915
Kind Code:
B2
Abstract:
PURPOSE: To considerably reduce a power consumption by cascading C-MOSs and feeding back the output of the C-MOS in a last stage to the gate of the C-MOS in a first stage.
CONSTITUTION: C-MOSs m1 to m3 are cascaded to constitue an operational amplifier, and input voltages V1 and V2 are inputted to the gate of the C-MOS 1 in the first stage through capacitors C1 and C2. The output of the C-MOS m1 is inputted to the gate of the C-MOS m2, and the output of the C-MOS m2 is inputted to the gate of the C-MOS m3, and the output of the C-MOS m3 is fed back to the gate of the C-MOS ml through a capacitor e3. In each of C-MOSs m1 to m3, a positive voltage VDD is applied to the drain of a PMOS, and a negative voltage VSS is inputted to the source of an nMOS. Thus, the output range of the C-MOS is -VSS to +VDD. A current directly flowing from VDD to VSS does not exist in this circuit constitution, and only the operation current for charging/discharging of an input capacity is consumed.
Inventors:
Kotobuki Guoliang
Yang Yasuyasu
Wiwat Wonwalla Wipat
Nao Takatori
Makoto Yamamoto
Yang Yasuyasu
Wiwat Wonwalla Wipat
Nao Takatori
Makoto Yamamoto
Application Number:
JP21823292A
Publication Date:
February 05, 2001
Filing Date:
July 24, 1992
Export Citation:
Assignee:
Takayama Co., Ltd.
Sharp Corporation
Sharp Corporation
International Classes:
H03F1/34; H03F1/02; H03F3/16; H03F3/30; (IPC1-7): H03F1/02; H03F1/34; H03F3/16; H03F3/30
Domestic Patent References:
| JP58137083A | ||||
| JP6150408A | ||||
| JP6481082A | ||||
| JP1129608A |
Attorney, Agent or Firm:
Yusuke Hiraki (1 person outside)