Title:
OSCILLATION CIRCUIT
Document Type and Number:
Japanese Patent JP3201339
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide a oscillation circuit with which both reduction of oscillation stabilizing time and suppression of power consumption are realized.
SOLUTION: This oscillation circuit is constituted by providing a crystal resonator between the input and output terminals of CMOS inverters 3 and 4. Transistors 5 and 6 for current control are provided on the power source side of the inverters 3 and 4, and both the transistors are controlled by transistors 7, 8 and 9 constituting a current mirror circuit. To the transistor 9 for control a current is supplied from a transistor 10, to the gate of which a charging/discharging voltage VG generated by a time constant circuit is applied. The currents of the transistors 5 and 6 can be controlled so as to be a peak current value at the time of starting oscillation through power supply and to be gradually decreased later, and quick stabilization of oscillation and suppression of power consumption can be attained.
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Inventors:
Yoshimasa Tanei
Application Number:
JP11011598A
Publication Date:
August 20, 2001
Filing Date:
April 07, 1998
Export Citation:
Assignee:
NEC
International Classes:
H03K3/02; H03B5/32; (IPC1-7): H03B5/32; H03K3/02
Domestic Patent References:
| JP11127032A | ||||
| JP5180751A | ||||
| JP5528633A | ||||
| JP653741A |
Attorney, Agent or Firm:
Yasuo Suzuki (1 person outside)