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Title:
OUT OF SYNCHRONISM DETECTION CIRCUIT
Document Type and Number:
Japanese Patent JPH02237334
Kind Code:
A
Abstract:

PURPOSE: To prevent mis-decision of detection for out of synchronism from generation by obtaining a threshold level for detecting out of synchronism based on the past value being the result of integrating counts of an inputted synchronous information pulse.

CONSTITUTION: A count A being the result of counting repetitively the number of synchronous information pulses SIP outputted from a Viterbi decoder 10 for a prescribed period is compared with a prescribed threshold level B, and when the count does not exceeds the threshold level B, it is discriminated to be in the synchronous state, and when the threshold level B is exceeded, it is discriminated to be in out of synchronism state. Then a binary counter 1 is provided, which counts the synchronous information pulse SIP and outputs the binary count A. Furthermore, a feedback type integration circuit 3 setting a feedback coefficient of a feedback loop feeding back to be multiplied with the stored value of the past count output counted by the counter 1 and adding the result to the input A is provided, and the output of the feedback integration circuit 3 is used as the threshold level B of the comparator 2. Thus, even when signal input/noise ratio is varied, the generation of mis-decision with respect to the pulse SIP is prevented.


Inventors:
MIYAMOTO BUNICHI
YAMASHITA ATSUSHI
Application Number:
JP5912589A
Publication Date:
September 19, 1990
Filing Date:
March 10, 1989
Export Citation:
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Assignee:
FUJITSU LTD
International Classes:
H04L7/00; H03L7/095; H04B7/212; (IPC1-7): H04B7/212; H04L7/00
Attorney, Agent or Firm:
Sadaichi Igita