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Patent Searching and Data


Title:
OUTPUT AMPLIFYING CIRCUIT
Document Type and Number:
Japanese Patent JPS5624812
Kind Code:
A
Abstract:

PURPOSE: To increase electric power conversion efficiency and to improve switching distortion by adjusting the idling current and power-feed retaining current of an output transistor by resistors.

CONSTITUTION: Output voltage Vout developed at the connection point between resistors (R) 20 and 21 with no load is set to OV and idling current IDC flowing through output transistor TR17, 19 is adjusted by R14. Next, R41 is so adjusted that when Vout≤-1V, electric current Ia flowing through TR17 is IDC+Iα (Iα is conduction retaining current of TR17, 19), and R45 is also adjusted so that when Vout≥1V, electric current Ib flowing through TR19 is IDC+Iα. When Vout=OV, idling current IDC flows through TR17, 19. Further, when Vout exceeds the absolute value of base-emitter voltage VBE of TR35, 36, TR17, 19 are held conductive.


Inventors:
KAMIMURA KAZUHIKO
Application Number:
JP10058279A
Publication Date:
March 10, 1981
Filing Date:
August 07, 1979
Export Citation:
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Assignee:
SONY CORP
International Classes:
H03F3/20; H03F3/30; (IPC1-7): H03F3/30
Domestic Patent References:
JPS5441055A1979-03-31