Title:
出力バッファー回路
Document Type and Number:
Japanese Patent JP5336635
Kind Code:
B2
Abstract:
PROBLEM TO BE SOLVED: To provide an output buffer circuit that suppresses increases in the area, volume and number of components of output buffers and improves drive capability.SOLUTION: In an output buffer circuit 1 having a first input path 4a for transmitting a first drive signal LIN, a second input path 4b for transmitting a second drive signal RIN, a first output buffer 6a corresponding to the first input path 4a, and a second output buffer 6b corresponding to the second input path 4b, input path switching means 8 electrically connects the first input path 4a to the first output buffer 6a and second output buffer 6b in a monaural mode out of stereo and monaural modes, and output path switching means 10 electrically connects the first output buffer 6a and second output buffer 6b to a first load 2a corresponding to the first input path 4a and first output buffer 6a.
Inventors:
Hideyuki Aizawa
Application Number:
JP2012146267A
Publication Date:
November 06, 2013
Filing Date:
June 29, 2012
Export Citation:
Assignee:
Asahi Kasei Electronics Co., Ltd.
International Classes:
H03F3/68; H03F3/187; H03F3/21; H03K17/00; H03K17/687; H03K17/693; H03K19/0175; H03K19/0948
Domestic Patent References:
| JP49046701A | ||||
| JP5226948A |
Attorney, Agent or Firm:
Tetsuya Mori
Megumi Konishi
Hide Tanaka Tetsu
Megumi Konishi
Hide Tanaka Tetsu