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Patent Searching and Data


Title:
OUTPUT BUFFER CIRCUIT
Document Type and Number:
Japanese Patent JPH06276081
Kind Code:
A
Abstract:

PURPOSE: To provide the output buffer circuit which makes a power source generate no noise while securing sufficient load driving ability.

CONSTITUTION: A P channel MOS transistor(TR) 1 and an N channel MOS TR2 are connected in series between a high-potential side power source Vcc and a low-potential side power source GND, and an input signal IN is inputted to the gates of both the TRs 1 and 2. Output signals OUT are outputted from the drains of both the TRs 1 and 2. A subordinate buffer circuit 2 which operates when the output signal OUT exceeds a previously set threshold value to increase the amplitude of the output signal OUT is connected to the main buffer circuit 1 composed of the TRs 1 and 2.


Inventors:
TANAKA MASAHIRO
Application Number:
JP6077793A
Publication Date:
September 30, 1994
Filing Date:
March 19, 1993
Export Citation:
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Assignee:
FUJITSU LTD
FUJITSU VLSI LTD
International Classes:
H03K17/16; H03K17/687; H03K19/0175; (IPC1-7): H03K19/0175; H03K17/16; H03K17/687
Attorney, Agent or Firm:
Hironobu Onda