Title:
OUTPUT BUFFER FOR SEMICONDUCTOR INTEGRATED CIRCUIT DEVICE
Document Type and Number:
Japanese Patent JP3209648
Kind Code:
B2
Abstract:
PURPOSE: To obtain the output buffer of the semiconductor integrated circuit device in which a prescribed output characteristic is obtained corresponding to two kinds of power supply voltages.
CONSTITUTION: The buffer has an NMOS transistor (TR) 2 and a PMOS TR 1 and one of sources or drains connect to a power line whose voltage is set to a Vcc or GND and the other of sources or drains are connected in common to be an output terminal. The point of the voltage Vcc is connected to the drain of the NMOS TR 2 in the high voltage operation and the point of GND is connected to the source of the PMOS TR 1, and the point of the Vcc is connected to the source of the PMOS TR 1 in a low voltage operation and the point of the GND is connected to the drain of the NMOS TR 2 through the changeover of the power line.
Inventors:
Ryuichi Matsuo
Toru Shiomi
Toru Shiomi
Application Number:
JP25246094A
Publication Date:
September 17, 2001
Filing Date:
October 18, 1994
Export Citation:
Assignee:
Mitsubishi Electric Corporation
International Classes:
H01L27/04; H01L21/822; H03K17/687; H03K19/00; H03K19/0175; H03K19/0948; (IPC1-7): H03K19/00
Attorney, Agent or Firm:
Soga Doteru (6 people outside)
Previous Patent: Combustion timber material log
Next Patent: INTERMEDIATE FOR PRODUCING INSECTICIDAL NITROIMINO OR CYANOIMINO COMPOUND
Next Patent: INTERMEDIATE FOR PRODUCING INSECTICIDAL NITROIMINO OR CYANOIMINO COMPOUND