PURPOSE: To attain a high speed operation of an output buffer by providing an auxiliary control part including a pulse generating circuit which is connected to the gate of a 2nd N channel MOS transistor TR and decides a conducting period of the 2nd N channel MOS TR and a drive circuit.

CONSTITUTION: In an auxiliary drive circuit G13, the output of an inverter 17 falls when a signal transmission delay time set by the inverters 15 - 17 after the rise of an input signal I11. At the same time, the output of a NAND gate is inverted to a VDD level and the output of an inverter 19 is inverted to a GND level together with an N channel MOS TR N12 turned off respectively. In such a case where an input signal falls, the N channel MOS TR N11 and N12 are turned on an a transient state. Then the TR N12 is turned off. As a result, the fall delay time is equal to the rise delay time and the undershoot of an output signal O11 is reduced. Thus a high speed operation is assured for an output buffer.