PURPOSE: To drive a load circuit under an optimum drive condition even when a load circuit of a next stage is modified by selecting a MOS transistor (TR) to drive the load circuit of the next stage with an external selection signal.

CONSTITUTION: When a selection signal given to a TR selection terminal 5 is at a high level, an output of a NOR gate 6 is always at a low level and an N-channel MOS TR Q2 is always turned off. On the other hand, a P-channel MOS TR Q4 is turned on/off depending on a level of a data inputted to an input terminal 3. Moreover, when the selection signal is at a low level, an output of a NAND gate 7 is always at a high level and the TR Q4 is always turned off. Furthermore, the TR Q2 is turned on/off depending on a level of a data inputted to an input terminal 3. Thus, even when any modification takes place in a load circuit connecting to a next stage, the circuit is driven with a signal amplitude in matching with the load condition.