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Title:
OUTPUT CIRCUIT
Document Type and Number:
Japanese Patent JP2014117063
Kind Code:
A
Abstract:

To provide an output circuit capable of preventing the occurrence of a through-current.

The output circuit in an embodiment comprises: a diode D1 in which an input voltage VDIN is applied to the drain terminal of an output-use NMOS transistor N100, an LC circuit and a regenerative diode D are connected to a source terminal OUT, and an anode terminal is connected to the gate terminal of the output-use NMOS transistor N100; an NMOS transistor N1 having its drain terminal connected to the cathode terminal of the diode D1 and its source terminal connected to a ground potential terminal GND; and an NMOS transistor N2 and an NMOS transistor N3 connected in series between the gate terminal and the source terminal of the output-use NMOS transistor N100. When the output-use NMOS transistor N100 is non-conductive, a control circuit 1 establishes electrical continuity between the NMOS transistor N2 and the NMOS transistor N3, and establishes electrical continuity to the NMOS transistor N1 for a period shorter than this conduction period.


Inventors:
YOSHINO HIROSHI
Application Number:
JP2012269137A
Publication Date:
June 26, 2014
Filing Date:
December 10, 2012
Export Citation:
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Assignee:
TOSHIBA CORP
International Classes:
H02M3/155
Domestic Patent References:
JP2010136532A2010-06-17
JP2009011045A2009-01-15
JP2012139096A2012-07-19
JP2005354586A2005-12-22
Foreign References:
WO2011079194A22011-06-30
Attorney, Agent or Firm:
Masayuki Sunai
Fujiwara Yasutaka
Hajime Yamashita



 
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