Title:
OUTPUT CIRCUIT
Document Type and Number:
Japanese Patent JPH0669776
Kind Code:
A
Abstract:
PURPOSE: To obtain the output circuit of low power consumption and a small occupation area.
CONSTITUTION: This circuit has first FETQ1 and second FETQ2. The characteristic of the circuit is that a first power source VSS is connected to the source of first FETQ1, a first bias power source VCS is connected to the gate of first FETQ1, the source of second FETQ2 is connected to the drain of first FETQ1, the input terminal of the output circuit TIN is connected to the gate of second FETQ2 and the output terminal TOUT of the output circuit is connected to the drain of second FETQ2.
Inventors:
TOGASHI MINORU
SUZUKI MASAO
SUZUKI MASAO
Application Number:
JP24144392A
Publication Date:
March 11, 1994
Filing Date:
August 19, 1992
Export Citation:
Assignee:
NIPPON TELEGRAPH & TELEPHONE
International Classes:
H03K17/687; H03K19/0175; (IPC1-7): H03K17/687; H03K19/0175
Attorney, Agent or Firm:
Masataka Kobayashi
Next Patent: FET SWITCH CIRCUIT