Title:
OUTPUT CIRCUIT
Document Type and Number:
Japanese Patent JPH11225062
Kind Code:
A
Abstract:
To provide an output circuit that suppresses variations in a delay time till a sent signal reaches a load.
Output buffer control circuits 313, 314 are placed between an internal circuit and a final stage output buffer circuit in this output circuit. An input signal from the internal circuit, and at least any one of a power supply voltage for the output buffer and a ground voltage for the output buffer are given to the output buffer control circuits 313, 314 to generate a control signal for a final stage output buffer circuit that is fluctuated with a fluctuation of the output buffer power supply voltage and the output buffer ground voltage.
Inventors:
SATO TAKASHI
FUKUI KENICHI
NISHIO YOJI
NAKAGOME YOSHINOBU
FUKUI KENICHI
NISHIO YOJI
NAKAGOME YOSHINOBU
Application Number:
JP2419298A
Publication Date:
August 17, 1999
Filing Date:
February 05, 1998
Export Citation:
Assignee:
HITACHI LTD
International Classes:
G11C11/409; H03K19/0175; (IPC1-7): H03K19/0175; G11C11/409
Attorney, Agent or Firm:
Ogawa Katsuo
Previous Patent: DEVICE AND METHOD FOR ADAPTING OUTPUT DRIVER OF INTEGRATED CIRCUIT TO PRESCRIBED SITUATION
Next Patent: PARTIALLY REWRITABLE PLD
Next Patent: PARTIALLY REWRITABLE PLD