PURPOSE: To decrease the level fluctuation of power supply and ground by connecting a resistor having a sufficient larger resistance than the conduction resistance of a drive transistor (TR) between the drive TR and an output TR.

CONSTITUTION: The conduction on-resistance of CMOS TRs Q3∼Q6 is selected sufficiently smaller than resistors R1, R2. The capability to drive output TRs Q1, Q2 depends on the resistances of the resistors R1, R2, the delay time when the gate input signal of the output TRs Q1, Q2 rises or descends is controlled by the resistors R1, R2 and kept nearly constant independently of the power potential. Thus, when the power potential is at a high level, the switching speed of the output TRs Q1, Q2 is increased, resulting in increasing the level fluctuation of power supply and ground levels and in incurring mis-recognition of the signal level given to an input terminal. Such defect is improved.