PURPOSE: To decrease the chip area of an integrated circuit by providing the 1st and 2nd switching circuits where the 1st and 2nd capacitive elements are connected in parallel and series respectively and also providing an FET operated with a discharge output of the 1st and 2nd capacitive elements.

CONSTITUTION: The capacitive elements C1, C2 are formed in the integrated circuit and analog switches S1, S2...S6 are provided. In bringing the level of a terminal Φ into logical "1", the switches S4∼S6 are turned on, the capacitive elements C1, C2 are connected in parallel and charged to a power supply voltage VDD. The switch S1 is also turned on and a transistor TRF1 is turned off. In bringing the level of a terminal Φ' to logical "1", the switches S2, S3 are turned on, the capacitive elements C1, C2 are connected in series and a voltage 2VDD is applied to the gate of the TRF1. Thus, a current flows to a load L, which is driven.