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Title:
OUTPUT DRIVING CIRCUIT
Document Type and Number:
Japanese Patent JPS58121830
Kind Code:
A
Abstract:

PURPOSE: To attain an output driving circuit of an integrated circuit using the output driving circuit as an input circuit at check.

CONSTITUTION: An input signal from an input terminal P1 is synthesized with a signal inverted at inverters X1, X2 and applied to a gate of E-FETs 5a, 5b, 6a, 6b complementarily. The source and drain of the E-FETs 5a, 5b, 6a, 6b are connected in series, the drain of the E-FETs 6a, 6b is connected to the source and gate of D-FETs 7a, 7b, and the drain of the D-FETs 7a, 7b is connected to a power supply. Since either one of the E-FETs 5a, 6a is set off without fail in terms of DC, no current flows from the power supply. In using the driving circuit as an input circuit, when the P1 is at a low potential, the FET 5a is set off and the 6a is set on, and when a low potential (e.g., ground potential) is given to an input terminal P2 in this state, a power supply voltage V is applied between the source and drain of the FET 7a.


Inventors:
KADOTA HIROSHI
ICHINOHE EISUKE
Application Number:
JP410282A
Publication Date:
July 20, 1983
Filing Date:
January 14, 1982
Export Citation:
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Assignee:
MATSUSHITA ELECTRIC IND CO LTD
International Classes:
H03K17/687; H03K19/0944; (IPC1-7): H03K17/687; H03K19/094
Domestic Patent References:
JPS5186952A1976-07-30
JPS5186959A1976-07-30
JPS5268304A1977-06-07
JPS5648721A1981-05-02
Attorney, Agent or Firm:
Toshio Nakao



 
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