To provide the output interface, through which data are transferred from a data source operated at a 1st clock rate to a data sink operated at a 2nd clock rate.
The output interface includes a 1st latch 1302 operated at an internal clock rate, a 2nd latch 1304 that is operated at an external clock rate and receives data from the 1st latch, a 1st signal generator that is operated at the internal clock rate and generates a data valid signal, a 3rd latch 1320 that receives a data valid signal from the 1st signal generator in response to an external clock signal, and a 2nd signal generator that is operated at the external clock rate and allows the 2nd latch to activate a load data signal, in response to the reception of the data valid signal from the 3rd latch. When the load data signal is active, the data are transferred from the 1st latch to the 2nd latch, in response to the reception of the external clock signal by the 2nd latch.
MACFARLANE CHARLES D
GAMMACK RICHARD J
JONES ANTHONY M
ROBBINS WILLIAM P
BARNES MARK
