Title:
PLL回路
Document Type and Number:
Japanese Patent JP4850959
Kind Code:
B2
Abstract:
A PLL circuit which can obtain a VCO output having satisfactory spurious output characteristics with respect to all channels and which can suppress the fluctuation of the characteristics due to a temperature change is disclosed. A control circuit 3 provides a frequency division ratio table 32 where frequency division ratios to improve spurious output characteristics in the output of a VCO for each channel number at temperatures are stored, and the control circuit reads, from the table 32, the frequency division ratio corresponding to the temperature detected by the temperature sensor 31 and an input channel number, to set the frequency division ratio in a PLL IC 2 and to set the channel number and the frequency division ratio in a DDS circuit 4. The DDS circuit 4 calculates the value of a reference frequency based on the channel number and the frequency division ratio to generate the reference frequency.
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Inventors:
Hiroki Kimura
Application Number:
JP2010081506A
Publication Date:
January 11, 2012
Filing Date:
March 31, 2010
Export Citation:
Assignee:
Nippon Denpa Industry Co., Ltd.
International Classes:
H03L7/183; H03L1/02
Domestic Patent References:
| JP10022825A | ||||
| JP7131343A | ||||
| JP2008193389A | ||||
| JP9008551A | ||||
| JP9018336A | ||||
| JP63035017A |
Attorney, Agent or Firm:
Nobuhiro Funatsu