Title:
PLL INCORPORATED DEVICE AND PLL INTERFERENCE PREVENTION METHOD
Document Type and Number:
Japanese Patent JP2017228891
Kind Code:
A
Abstract:
PROBLEM TO BE SOLVED: To prevent interference between PLL circuits without changing a frequency of an output signal of the PLL circuits independently of an individual difference of a device and the like.SOLUTION: Provided is a PLL incorporated device 1 that comprises at least two PLL circuits including a first PLL circuit 10 and a second PLL circuit 20, and that prevents interference of the PLL circuits by changing settings of these PLL circuits 10 and 20. The PLL incorporated device 1 comprises a first setting unit 31 that sets frequencies of a first VCO 17 and a second VCO 28 so that a frequency fc1 of the first VCO 17 included in the first PLL circuit 10, a frequency fc2 of the second VCO 28 included in the second PLL circuit 20, a band width fw1 of the frequency of the first VCO 17, and a band width fw2 of the frequency of the second VCO 28 satisfy a relation of {|fc1-fc2|-(fw1+fw2)/2≥α}.SELECTED DRAWING: Figure 1
Inventors:
NAGATA MITSURU
Application Number:
JP2016122742A
Publication Date:
December 28, 2017
Filing Date:
June 21, 2016
Export Citation:
Assignee:
NIPPON SYST WEAR KK
International Classes:
H03L7/07; H03L7/089
Domestic Patent References:
| JP2001309135A | 2001-11-02 | |||
| JP2007295363A | 2007-11-08 | |||
| JPH08102667A | 1996-04-16 | |||
| JPH1056381A | 1998-02-24 | |||
| JPS6359223A | 1988-03-15 |
Foreign References:
| US20060033546A1 | 2006-02-16 |
Attorney, Agent or Firm:
Tomihiko Isono