Title:
【発明の名称】読み出し専用メモリ装置の製造方法
Document Type and Number:
Japanese Patent JP2797538
Kind Code:
B2
Abstract:
PURPOSE:To obtain a highly integrated read only memory by forming a plurality of electrode layers which are extending in the approximately vertical direction on a thin insulating film between thick insulating films, selectively introducing impurities on the surface of a semiconductor substrate at the lower part, and forming a program. CONSTITUTION:A plurality of first polysilicon layers 103 which are the first electrode layers in parallel strip patterns are formed in the X direction which is orthogonally intersected with a thick oxide film 102. Second polysilicon layers 104 which are the second electrode layers are formed. The first polysilicon layers 103 are formed in the parallel strip pattern, and an interval l1 is provided between the neighboring patterns. A part of the edge part of the second polysilicon layer 104 in the Y direction is overlapped on the edge part of the first polysilicon layer 103 at the same plane. Therefore, memory transistors are formed in parallel without the interval in the Y direction. An approximately square pattern 105 is the window part of a mask for a program formed by ion implantation in the lower part of the first polysilicon layer 103.
Inventors:
Akira Nakagawara
Application Number:
JP28016189A
Publication Date:
September 17, 1998
Filing Date:
October 27, 1989
Export Citation:
Assignee:
ソニー株式会社
International Classes:
H01L27/112; H01L21/8246; (IPC1-7): H01L21/8246; H01L27/112
Domestic Patent References:
| JP5375781A | ||||
| JP59139668A | ||||
| JP2205073A | ||||
| JP387063A | ||||
| JP6430260A | ||||
| JP1258464A |
Attorney, Agent or Firm:
Akira Koike (1 person outside)