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Title:
PACKAGE FOR SEMICONDUCTOR CHIP, MOUNTING/REMOVING AND TESTING PACKAGE, AND JIG THEREFOR
Document Type and Number:
Japanese Patent JPH03120740
Kind Code:
A
Abstract:

PURPOSE: To enable miniaturization and multiple lead usage without narrowing the spacing between surface mounting leads by comprising the leads for use in the surface mounting and external contacts exposed outside a package which are capable of being heated and/or can be used for signal observation.

CONSTITUTION: Surface mounting leads 12 are aligned and arranged on the bottom of a package 11 except a semiconductor chip mounting part 13. Further, equally spaced mounting and inspecting external contacts 14 are arranged in one column on the side surface of the package 11, and the extremities of the leads are bent. The leads 12 and the external contacts 13 are connected each other internally so that mounting and inspection of the package 11 can be carried out by using the external contacts 13. The leads 12 are arranged on he whole bottom surface of the package 11 except a semiconductor chip mounting part 13, but because surface mounting is carried out, the spacing between the leads can be made smaller than the pin spacing in the conventional pin grid array. Further, the external contacts 14 are arranged on the side surface of the package with narrower spacing than the leads 12, but they have no relation to the solder bridge, mounting position shift, etc.


Inventors:
OKAZAWA KOICHI
Application Number:
JP25766889A
Publication Date:
May 22, 1991
Filing Date:
October 04, 1989
Export Citation:
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Assignee:
HITACHI LTD
International Classes:
H01L21/66; H01L23/50; H05K1/18; H05K3/34; G01R31/26; (IPC1-7): G01R31/26; H01L21/66; H01L23/50; H05K1/18; H05K3/34
Attorney, Agent or Firm:
Katsuo Ogawa (1 person outside)



 
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