PURPOSE: To prevent delay of an external clock signal in a package structure for a synchronous DRAM which is operated in response to an external clock to be input from an exterior.
CONSTITUTION: A package structure for a synchronous DRAM has a plurality of DRAM cores formed at a chip 21, pads 24a-1-24a-5, 24b-1-24b-3, etc., for inputting external clocks CLK, CKE in such a manner that data are output from the cores at a predetermined timing synchronized with the clocks CLK, CKE, and comprises clock leads 23a, 23b connected to the clocks CLK, CKE. The leads 23a, 23b are led to the vicinity of arranged positions of the pads 24a-1-24a-5, 24b-1-24b-3, etc., for inputting the clocks in a roundabout manner and connected in the state that arranged near the leads 23a, 23b.
YANAGISAWA MAKOTO
HATAKEYAMA ATSUSHI
KODAMA YUKINORI
OGAWA JUNJI
TAKEMAE YOSHIHIRO
MOCHIZUKI HIROHIKO
TAGUCHI MASAO
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