Login| Sign Up| Help| Contact|

Patent Searching and Data


Title:
PACKET EXCHANGE NODE
Document Type and Number:
Japanese Patent JPH02228845
Kind Code:
A
Abstract:

PURPOSE: To improve the throughput of packet exchange by using a logical channel constituted with the hardware comprising a memory, a gate and a decoder to exchange message packets.

CONSTITUTION: A packet exchange node is provided with a logical switch send ing a message packet stored in reception buffers 21-23 to transmission buffers 31-33 corresponding to communication lines represented by its transmission destination address or terminal equipments 61-63. Then the logical channel switch consists of deccders 71-73, output buffers 811-813, 821-823, 831-833, OR gates 911-913, 921- 923, 931-933 and 101-103. Thus, the exchange of message packets is implemented by the hardware mainly comprising memories, gates and decoders. Thus, the throughput of the packet exchange is improved.


Inventors:
TAKAHASHI KAZUO
Application Number:
JP5113389A
Publication Date:
September 11, 1990
Filing Date:
March 02, 1989
Export Citation:
Click for automatic bibliography generation   Help
Assignee:
NEC CORP
International Classes:
H04L12/70; (IPC1-7): H04L12/56
Attorney, Agent or Firm:
Shin Uchihara



 
Previous Patent: LONG PACKET CONTROL SYSTEM

Next Patent: CMI CODING CIRCUIT