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Title:
PACKET EXCHANGE SYSTEM
Document Type and Number:
Japanese Patent JPH03238950
Kind Code:
A
Abstract:

PURPOSE: To reduce the production rate of missing packet data mistransfer by using a frame check sequence so as to check only basic information or only a packet header part when an undefined bit allocation of a control part of a received packet format is detected.

CONSTITUTION: Upon the receipt of a start flag sequence 41 from a reception line 5, a zero elimination reception section 14 deletes a start flag sequence 41 and a code string after a succeeding address part 42 is converted into a parallel code and sent to an additional data analysis section 15. The additional data analysis section 15 sends a delete inhibit signal to the zero elimination reception section 14 when the received control part 43 is an audio video packet. Thus, elimination of a code 0 specified by the international standard is not implemented from basic information and additional information and the result is transferred from the zero elimination reception section 14 to the additional data analysis section 15. Moreover, the additional data analysis section 15 checks only the received basic information 48 by using a frame check sequence 45. Since number of codes of the basic information 48 is less, the rate of defective check is less.


Inventors:
MARUYAMA MASAKO
Application Number:
JP3519990A
Publication Date:
October 24, 1991
Filing Date:
February 16, 1990
Export Citation:
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Assignee:
NEC CORP
International Classes:
H04L12/70; (IPC1-7): H04L12/56
Attorney, Agent or Firm:
Shin Uchihara



 
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