Title:
パケット処理装置、パケット制御方法及びパケット制御プログラム
Document Type and Number:
Japanese Patent JP5007703
Kind Code:
B2
Abstract:
A packet processor having one or two or more packet processing units is provided with a packet detector which detects whether or not a packet exists in a packet processing unit, and outputs a packet detection signal indicating a result of the detection, and a clock frequency controller which controls a clock to be supplied to the packet processing unit based on the packet detection signal.
Inventors:
Hisamatsu Hidenori
Application Number:
JP2008131001A
Publication Date:
August 22, 2012
Filing Date:
May 19, 2008
Export Citation:
Assignee:
NEC
International Classes:
H04L13/08; H04L7/00; H04L12/70
Domestic Patent References:
| JP2002237760A | ||||
| JP7336410A | ||||
| JP2005310100A | ||||
| JP2007228491A | ||||
| JP2007074607A | ||||
| JP10242992A | ||||
| JP2003069607A |
Attorney, Agent or Firm:
Kihei Watanabe