Title:
PACKET TRANSMISSION SYSTEM
Document Type and Number:
Japanese Patent JP3203978
Kind Code:
B2
Abstract:
PURPOSE: To match respective bit stream speeds on transmission and reception sides by periodically transmitting the bit stream of optional speed and format after adding the time of the position of a leading bit to a packet and to read it from a FIFO matched with the speed by the time on the reception side.
CONSTITUTION: On the transmission side, the inputted bit stream(BS) (a) is written in the FIFO in synchronism with the clock (b) of 4MHz and a counter outputs a value (t) for which the clock (b) is counted. Also, a sync time(ST) imparting circuit A uses a P1394 I/F circuit or the like and the value (t,) reads the BSa from the FIFO and outputs the packet P1/P2 for which ST is added/not added to the head. On the reception side, the packet received in the P1394 I/F circuit is written in the FIFO and it is read matched with the speed of the BSa on the transmission side by using the ST extracted in an ST extraction circuit. Thus, the RSa of the optional speed and format is received without depending on applications.
Inventors:
Tomohisa Shiga
Application Number:
JP24225594A
Publication Date:
September 04, 2001
Filing Date:
September 09, 1994
Export Citation:
Assignee:
ソニー株式会社
International Classes:
G06F13/42; H04J3/06; H04L7/00; H04L12/40; H04Q11/04; H04L12/64; (IPC1-7): H04L7/00; H04J3/06; H04L12/40
Domestic Patent References:
| JP537560A | ||||
| JP4162840A | ||||
| JP5843099A | ||||
| JP5634252A |
Other References:
【文献】米国特許5052029(US,A)
Attorney, Agent or Firm:
Akira Koike (2 outside)