Title:
PAL SYSTEM CHROMINANCE SIGNAL PROCESSING CIRCUIT
Document Type and Number:
Japanese Patent JPS6387094
Kind Code:
A
Abstract:
PURPOSE:To attain a stable PAL matrix processing by detecting a phase difference and a amplitude difference between a one line delay burst signal and a direct burst signal and conforming with phases and conforming with amplitudes automatically. CONSTITUTION:Into an input terminal 11, a PAL chroma signal composed of a burst signal and a carrier chrominance signal is inputted. The signal is supplied through a band amplifier 12 to a 1H delaying line. An 1H delaying signal is simultaneously added to a phase shifter 14, a phase detector 15 and a peak detector 16, and a direct signal is simultaneously added through a partial pressure circuit to the phase detector 15, the peak detector 16 and a gain control circuit 17. By the phase detector 15, the phase difference between the 1H delay signal and the burst period signal of the direct signal is detected, and the output control signal is sent to the phase shifter 14 and the phase shifting quantity of the 1H delaying signal is controlled. By the peak detector 16, the amplitude difference between the 1H delaying signal and the direct signal is detected, the detecting signal is added to a gain control circuit 17 and the gain control of the direct signal is executed.
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Inventors:
ADACHI TAKESHI
Application Number:
JP23229186A
Publication Date:
April 18, 1988
Filing Date:
September 30, 1986
Export Citation:
Assignee:
TOSHIBA CORP
International Classes:
H04N9/64; (IPC1-7): H04N9/64
Attorney, Agent or Firm:
Susumu Ito