Title:
PAPALLEL-SERIES CONVERTER
Document Type and Number:
Japanese Patent JPH01133427
Kind Code:
A
Abstract:
PURPOSE: To accelerate the operation speed of a parallel/serial converter by performing the detection of the parallel loading request conditions of a shift register and the setting to a parallel loading mode of the register in the different periods of clock signals. CONSTITUTION: In the case of performing the conversion of 8:1, when a selection signal SEL2 is made low, the signals SELs 1, 3 and 4 are made high and the shift of the data of a shift register 10 is started, the data are shifted out by 4 bits each from the output of B7, B15, B23 and B31. At the time, the shift is performed synchronized with the respective clock beats of the clock signals CLK and '1' accompanying a series of '0' is shifted from signals D to the register 10. Then, when a state where the signals D and B0-B4 are all '0' is detected in an NOR 22 at a certain clock bit, the signal S is made low (the parallel loading mode) at the next clock beat and the data are parallelly loaded from an input register 12 to the register 10 at the next clock beat.
Inventors:
RICHIYAADO JIEIMUSU HANPUREMAN
Application Number:
JP17501287A
Publication Date:
May 25, 1989
Filing Date:
July 15, 1987
Export Citation:
Assignee:
AKUTEIBU MEMORY TECHNOL LTD
International Classes:
H03M9/00; (IPC1-7): H03M9/00
Attorney, Agent or Firm:
Masao Okabe
Previous Patent: COMPRESSED DATA EDITING DEVICE
Next Patent: CUTTER PIN FALL-OUT PREVENTIVE STRUCTURE
Next Patent: CUTTER PIN FALL-OUT PREVENTIVE STRUCTURE