Title:
Parallel bit interleaver
Document Type and Number:
Japanese Patent JP6254671
Kind Code:
B2
Abstract:
Bit interleaving method for interleaving a QC-LDPC codeword made up of N cyclic blocks each consisting of Q cyclic block bits and the constellation word being made up of M bits with N being not a multiple of M. The bit interleaving comprises a cyclic block permutation step, a bit permutation step and a dividing step, where a first rule is applied to the N-N' cyclic blocks, with N' = N -X and X = rem(N, M) and a second rule is applied to the X cyclic blocks. After the cyclic block permutation process and according to the first rule, the N' cyclic blocks are divided so that the Q bits in each of the N' cyclic block are each allocated to a bit of an identical bit index in Q constellation words and the Q constellation words are each made up of one bit from each of M different cyclic blocks, said M different cyclic blocks being common to said Q constellation words.
Inventors:
Petrov Mikhail
Application Number:
JP2016256058A
Publication Date:
December 27, 2017
Filing Date:
December 28, 2016
Export Citation:
Assignee:
Panasonic Corporation
International Classes:
H03M13/19; H03M13/27
Domestic Patent References:
| JP2009153109A |
Foreign References:
| US20120189079 | ||||
| WO2010039257A1 |
Attorney, Agent or Firm:
Patent business corporation Nakajima intellectual property integrated office
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