To attain a counter circuit with small increase in the circuit scale in the case of the increase in the number of parallel data and a count number with respect to a counter circuit which counts the total number of numbers 1 or 0 in parallel data that is synchronized with a clock and is inputted.

This circuit is provided with an analog adding means 2 which adds voltage of plural signal lines in an analog manner and outputs added voltage, a converting means 3 which converts a voltage value of the added voltage into a digital value and outputs addition data, an integrating means 4 which digitally integrates the addition data and outputs lower integration data of lower prescribed bit width of an integration result and a carry showing overflow from the prescribed bit width, and a counting means 5 which counts the number of carry occurrences and outputs carry count value.