Title:
PARALLEL INTERFACE DEVICE
Document Type and Number:
Japanese Patent JPS6353602
Kind Code:
A
Abstract:
PURPOSE:To communicate interlocking information at a high speed by providing an interface circuit to transmit and receive an interlocking signal besides the circuit of transmitting and receiving hand shake data and obtaining a mechanical interlocking. CONSTITUTION:A microcomputer 11 decodes output data signals OD 0-5, input data signals ID 0-5, hand shake signals ODS and IDR, interlocking input signals II 0-3 and output signals ID 0-3 through a parallel interface circuit PIO 12 and executes the corresponding processing. The computer 11 accesses a port A of a PIO 12, outputs the signals OD 0-5 and the signals ODS and IDR on a bus, accesses a port B, inputs the signals ID 0-5 and the signals IDS and ODR, accesses a port C and inputs and outputs signals OI 0-3 and signals II 0-3 and ID 0-3. Ports A, B and C are connected through bus transceivers 13, 14, 15 and 16 with respective signals.
Inventors:
TASHIMO HIROSATO
Application Number:
JP19557886A
Publication Date:
March 07, 1988
Filing Date:
August 22, 1986
Export Citation:
Assignee:
OKI ELECTRIC IND CO LTD
International Classes:
G05B9/02; (IPC1-7): G05B9/02
Attorney, Agent or Firm:
Hiroshi Kikuchi