PURPOSE: To relieve the physical limitation and to process the date at a high speed by providing plural instruction processing mechanisms and a cache memory and integrating them in a single chip.

CONSTITUTION: A pair of a more significant address contained in a secondary cache memory 2 and the data are read out with a less significant address sent from a microprocessor 1. Then the reed-out more significant address is compared with another more significant address by a comparator 2B. If no coincidence is obtained between both addresses, the microprocessor 1 sends an address to a system bus 8 and reeds the data out of a main storage 4. At the same time, this data is written in the memory 2. If the microprocessor 1 detects a special instruction at execution of an instruction, an instruction is sent from a coprocessor 3 through a bus 7. Then the coprocessor 3 carries out the instruction.