Title:
PARALLEL PROCESSING SYSTEM
Document Type and Number:
Japanese Patent JP2858190
Kind Code:
B2
Abstract:
PURPOSE: To attain flexible system structure and rapid processing by simultaneously executing transmission/reception and through repeating between optional processor elements in a parallel processing system.
CONSTITUTION: Processor elements constituting the parallel processing system are provided with plural by-pass buses 42a to 42h capable of connecting plural communication channels CH1 to CH8 in common. Each of communication lines 6 for connecting respective communication channels CH1 to CH8 to other processor elements PE are connected to one bus out of an internal system bus 50 and by-pass buses 42a to 42h through a channel mode switching means 45 or 47. The means 45, 47 are switched in accordance with a command outputted from a managing processor 4. Since the processing operation of respective processor elements is executed synchronously with the same synchronizing signal, overhead time can be shortened and through-put can be improved.
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Inventors:
ONO HARUMICHI
SHIMIZU NORIKAZU
MATSUMOTO YOSHIAKI
UNNO TAKUO
WATANABE HIROSHI
SHIMIZU NORIKAZU
MATSUMOTO YOSHIAKI
UNNO TAKUO
WATANABE HIROSHI
Application Number:
JP23465392A
Publication Date:
February 17, 1999
Filing Date:
September 02, 1992
Export Citation:
Assignee:
HITACHI SEISAKUSHO KK
HITACHI JOHO SEIGYO SHISUTEMU KK
HITACHI JOHO SEIGYO SHISUTEMU KK
International Classes:
G06F15/173; G06F15/16; G06F15/177; G06F15/80; (IPC1-7): G06F15/177; G06F15/16
Domestic Patent References:
| JP6370345A |
Attorney, Agent or Firm:
Unuma Tatsuyuki
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