PURPOSE: To emulate a serial pseudo random number string generator or a scramble output by a parallel realizing configuration by providing a plurality of outputs which apply the continuous serial outputs of the serial pseudo random number string generator.
CONSTITUTION: Plural stages constituted as a shift register 22 are integrated in a typical serial pseudo random number string generator 20 (serial PRG) so that values at each stage can be transmitted to next stage until the final one. The values at the final stage are typically exclusive OR(XOR) calculated with one bit of a communication data stream, and the result of the XOR calculation is actually transmitted in a communication task. In the exclusive OR arithmetic operation, when both inputs are a logical value 1 or logical value 0, the output is defined a logical value 0, and when the inputs are a logical value 1 and 0 each, or vice verse, the output is defined a logical value 1.
UIRIAMU BAANAADO UEBAA
JIYORUJIYU ANDORE SHIYARURU RO
